Pci Express Base Specification Revision 60 Pdf -

The headline feature of PCI Express Base Specification Revision 6.0 is the doubling of data transfer rate to 64 Gigatransfers per second (GT/s) per lane.

To put this in perspective:

For a x16 slot (typically used for graphics cards), this provides a raw duplex throughput of approximately 256 GB/s in each direction. That is enough to transfer the entire contents of a 100GB Blu-ray disk in under half a second. pci express base specification revision 60 pdf

However, achieving 64 GT/s over copper traces on a motherboard is not trivial. This required a radical shift in how PCIe encodes data.

Instead of two voltage levels, PAM4 uses four distinct levels: The headline feature of PCI Express Base Specification

With four levels, PAM4 transmits two bits per single symbol period—doubling the data rate without doubling the clock frequency.

| Application | Why PCIe 6.0 is needed | |-------------|------------------------| | AI/ML accelerators | Massive inter-GPU and GPU-CPU bandwidth | | 400 GbE network cards | Match network line rates without bottlenecks | | CXL (Compute Express Link) 3.0 | CXL is built on PCIe 6.0 physical/logical layers | | Automotive (ASIL-B, ASIL-D) | FEC and CRC improve reliability for autonomous driving | | NVMe SSDs | Next-generation SSDs surpassing 32 GB/s | For a x16 slot (typically used for graphics

The PCI Express Base Specification Revision 6.0 was officially released in January 2022. It doubles the data rate of PCIe 5.0, moving from 32 GT/s (Giga-transfers per second) to 64 GT/s.

But raw speed is only half the story. To achieve this doubling without melting your motherboard traces, PCI-SIG had to reinvent the wheel on how data is encoded and protected.

Here are the four pillars of the revision:

If you are designing the next storage controller or network interface card (NIC), the PHY layer has changed dramatically. You need the spec to implement the PAM4 SerDes (Serializer/Deserializer) and the dedicated FEC logic.