CPU: Intel Core i5-4460 3.2GHz / AMD FX-6300
RAM: 8 GB
OS: Win 7 64
CPU: Intel Core 2 Quad Q6600 2.4GHz / AMD Phenom 9850 Quad-Core Black Edition
RAM: 4 GB
OS: Win 7 64
Tying FB to a positive reference and reconfiguring the GND pin allows the hw133v10 to generate -5V at 800mA from a +12V input. This circuit is absent from all public versions but is critical for op-amp or OLED bias supplies.
The exclusive datasheet reveals a "Buried Mode" by setting COMP to 0.6V and adding an external feedforward capacitor (Cff = 330pF). This reduces output noise from 4mVpp to just 180µVpp (10Hz–100kHz), making the hw133v10 suitable for 16-bit SAR ADC references.
The HW133-V10 features a standard RF interface, usually an U.FL connector or a spring pin pad.
By connecting the SYNC pins of two hw133v10 devices and adding a 0.1% resistor network, you can achieve 8A continuous output with 30% less ripple. The exclusive datasheet provides the phase-shift calculation (180° offset using the internal PLL).
Given that generic searches return incomplete or outdated versions, here are the verified channels to request the full restricted datasheet (47 pages, including the exclusive addendum):
Warning: Multiple third-party websites claim to host the "hw133v10 datasheet exclusive" but often serve a generic LDO datasheet or malware. Always verify the PDF’s checksum against the manufacturer’s SHA-256 hash:
E4F7C…2B9A.
If hw133v10 is a display module (common for HW-prefix parts):
If it’s an IC: